1. Field of the Invention
The present invention relates to a memory control device and a memory control method for performing data access to a memory.
2. Description of the Related Art
In recent years, with an increase in memory capacity, NAND flash memories excellent in a bit unit price are widely used. In the NAND flash memories with increased memory capacity and high integration, problems such as aging degradation of written data and incorrect data read due to concentrated reading operation have become obvious. These problems occur when electric charges that hold data are reduced with a lapse of years and/or when saved data are destroyed by a small amount of charges accumulated in adjacent memory cells through read operation.
To avoid such failures, a process of correcting an error portion of data is performed by adding an error correcting code (ECC), which corrects a data error, to the data, and writing and reading the data together with the ECC. However, the number of bits correctable by using the correcting code is limited. When the number of error bits is more than the correctable limit, error correction is no longer effective. This makes it necessary to detect and correct an error before the number of error bits exceeds the correctable limit. Accordingly, an apparatus has been devised to implement a method for detecting an error before the number of error bits exceeds the correctable limit (for example, Japanese Patent Application Laid-Open No. 2011-128751). In this apparatus, memory check is performed when normal data read is not performed so as to determine whether or not a refresh process is necessary.
In this apparatus, memory check is performed at the time of standby of a memory (at the time of idling) to determine a region that needs a refresh process. However, even if the memory is in a standby state at the time of starting memory check, data read may be requested in the midst of the memory check process thereafter. In such a case, a data read process needs to be performed after the memory check process is completed, which disturbs memory operation, causing such a problem as delayed data read process.